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1.2. PB926EJ-S architecture

The major components on the platform are:

  • ARM926EJ-S PXP Development Chip equipped with:

    • ARM926EJ-S processor that supports 32-bit ARM and 16-bit Thumb instructions sets and includes features for direct execution of Java byte codes. Executing Java byte codes requires the Java Technology Enabling Kit (JTEK)

    • Tightly-Coupled Memory (TCM) for code (32KB) and data (32KB)

    • cache memory for code (32KB) and data (32KB)

    • Memory Management Unit (MMU)

    • Multi-layer bus matrix that gives highly efficient simultaneous transfers

    • MOVE™ video encoding coprocessor

    • MBX graphics accelerator

    • Multi-Port Memory Controller (MPMC) for direct connection to dynamic memory

    • Synchronous Static Memory Controller (SSMC) for direct connection to static (SRAM or flash) memory

    • VFP9 Vector Floating Point coprocessor

    • two external AHB master bridges and one external AHB slave bridge

    • AHB monitor for detailed analysis of bus activity

    • System Controller

    • DMA controller

    • Vectored Interrupt Controller (VIC)

    • Color LCD controller (CLCDC)

    • Three UARTs,

    • Synchronous Serial Port (SSP)

    • Smart Card Interface (SCI)

    • Four eight-bit GPIOs

    • Real Time Clock (RTC)

    • Two programmable timers

    • Watchdog timer

    • Embedded Trace Macrocell (ETM9)

    • Embedded-ICE logic for JTAG debugging

    • Phase-Locked Loop (PLL)

    • Configuration Block.

  • Field Programmable Gate-Array (FPGA) that implements:

    • SSP, Smart Card, two MMC/SD card, UART, and two KMI controllers

    • configuration registers

    • interface to onboard Ethernet controllers

    • interface to onboard audio CODEC

    • interface to onboard On-the-Go (OTG) USB controller (three connectors)

    • registers for status, ID, onboard switches, LEDs, and clock control

    • a secondary interrupt controller and external DMA control logic

    • interface to PCI bus (for expansion through optional PCI expansion enclosure).

  • 128MB of 32-bit wide SDRAM

  • 2MB of 32-bit wide static RAM

  • 128MB of 32-bit wide NOR flash (two devices)

  • up to 320MB of static memory in an optional static memory expansion board

  • up to 256MB of SDRAM in an optional dynamic memory expansion board

  • programmable clock generators

  • connectors for VGA, color LCD display interface board, PCI, UART, GPIO, keyboard, mouse, Smart Card, USB, audio, MMC, SSP, and Ethernet

  • RealView Logic Tile connector (one or more optional RealView Logic Tiles can be used to develop custom IP)

  • debug and test connectors for JTAG, AHB monitor, ChipScope, and Trace port

  • DIP switches and LEDs

  • 2 row by 16 character LCD display

  • power conversion circuitry

  • Real-Time Clock (RTC)

  • time of year clock with backup battery.

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