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3.4. Clock architecture

The clock domains for the Versatile/AB926EJ-S are shown in Figure 3.15.

Figure 3.15. Clock distribution

Clock distribution

The main reference for the system is the 24MHz crystal connected to the programmable oscillator OSC0. A 24MHz clock from the bypass output of the oscillator OSC0 is used for:

Reference for OSC0 programmable oscillator

The 24MHz clock is the reference for the OSC0 programmable oscillator. The programmable output of OSC0 is normally used as XTALCLK and distributed to the FPGA, Ethernet logic, and the ARM926PXP development chip.

The FPGA contains clock control logic that can set the frequency of the programmable clock generators in OSC0 and OSC1.

Reference for OSC1 programmable oscillator

The 24MHz clock is also the reference for the OSC1 programmable oscillator. The programmable output of OSC1 is used as the bit clock for the CLCD controller in the ARM926PXP development chip.

ARM926PXP development chip peripherals

The SSP and SCI peripherals inside the use the 24MHz reference directly. The Timer uses a 1MHz clock derived from the 24MHz reference.

Alternative ARM926PXP development chip PLL clock

The ARM926PXP development chip normally uses the programmable output of OSC0 as the reference clock for the CPU, bus, and memory clock dividers. The System Controller in the ARM926EJ-S development chip can select the 24MHz clock signal on PLLCLKEXT, however, as an alternative source.


The USB uses the 24MHz clock for bus and interface timing.


A buffered version of HCLKM2 is used as a reference frequency for the controller interface to the FPGA.

In addition to the 24MHz reference and the outputs from the programmable oscillators, the following reference clocks are also present:

24.576MHz output Audio CODEC

The Audio CODEC has a dedicated crystal oscillator. The reference clock from the CODEC is connected to the AACI in the FPGA.

32kHz external RTC reference

There is an external real-time clock clocked by a dedicated 32kHz crystal oscillator. The external RTC interfaces with the FPGA over a serial bus.

32kHz oscillator module

A 32kHz oscillator modules outputs the REFCLK32K clock to the RTC inside the ARM926PXP development chip.

External XTALCLK from interface board

XTALCLK is normally sourced from OSC1, however resistor links R79 and R368 allow it to be sourced from the interface board.

25MHz Ethernet oscillator

The Ethernet controller has a 25MHz dedicated crystal oscillator for timing signals to and from the Ethernet connector.

6MHz USB debug oscillator

The USB debug interface has a dedicated 6MHz oscillator (not shown in Figure 3.15).

The clocks and clock-related logic are described in the following sections:


The default values for clock selection and frequency are appropriate for most situations.

Changing the clock divider options requires modifying the HDL inside the FPGA.

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