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3.8. Ethernet interface

The Ethernet interface is implemented with a SMC LAN91C111 10/100 Ethernet single-chip MAC and PHY. This is provided with a slave interface to the system bus by the FPGA.

The internal registers of the LAN91C111 are memory-mapped onto the AHBM2 bus and occupy 16 word locations at 0x10010000.

The isolating RJ45 connector incorporates two network status LEDs. The function of the LEDs can be set to indicate link, activity, transmit, receive, full duplex, or 10/100 selection. See the data sheet for the LAN91C111 for more details on programming the registers.

The architecture of the Ethernet interface is shown in Figure 3.21.

Figure 3.21. Ethernet interface architecture

Ethernet interface architecture

Table 3.9. Ethernet signals
USBETHD[31:0]Data lines to USB and Ethernet controllers
USBETHA[8:2]Address lines to USB and Ethernet controllers
ETHA[15:13]Address lines to Ethernet controller
ETHnBE[3:0]Byte-enable signals to Ethernet controller
TPO+, TPO-Signal from controller to Ethernet interface
TPI+, TPI-Signal from Ethernet interface to controller
LEDA, LEDBActivity indicator LEDs. The function of the LEDs can be configured by writing to a LAN91C111 register.
ETHRESETReset signal to LAN91C111 (buffered and inverted nRESET)
ETHARDYAsynchronous ready signal
ETHSRDYSynchronous ready signal
ETHnRDYRTNSignals to the controller to complete synchronous read cycles
ETHnADSLatches address to controller
LCLKClock to controller interface
ETHnRDRead signal for asynchronous interface
ETHnWRWrite signal for asynchronous interface
ETHnDATACSEnables accesses to the controller data path
ETHnCYCLEUsed to control EISA bust mode synchronous cycles if LOW
ETHnLDEVAsserted LOW if AEN is low and the address lines decode to the controller address programmed into the base address register
ETHWnRDefines bus direction for synchronous accesses
ETHnVLBUSThis signal is connected to ground by a pull-down resistor. If LOW, the controller uses VL bus accesses. If HIGH, the controller uses EISA DMA accesses.

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