The ARM926PXP development chip contains the primary interrupt controller and a secondary interrupt controller is in the FPGA, see Figure 3.23.
The primary interrupt controller manages interrupts from internal devices and provides six pins for use by the external secondary interrupt controller present in the FPGA. VICINTSOURCE31 is the output from the secondary controller. VICINTSOURCE[26:21] can be driven from individual interrupt signals from peripherals in the FPGA. VICINTSOURCE[28:27] can be driven from the interface connector.
For details on the programming model for the interrupt controllers, see:
the ARM926EJ-S Development Chip Reference manual
the ARM PrimeCell Vector Interrupt Controller (PL190) Technical Reference Manual manual