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3.3.3. Reset level

Table 3.3 lists the default levels of reset that results from external sources.

Table 3.3. Reset sources and effects
External sourceReset levelHardware nBOARDPOR generatedReset generatedfor CPU, memory and peripherals
Power on0YesYes
RESET pushbutton or software reset6NoYes

Figure 3.11 shows the activity on the reset signals at different levels of reset.

The level of reset that results from pressing the RESET pushbutton or generating a software reset can be configured by the SYS_RESETCTRL register. The ability to configure the reset level gives greater flexibility in designing applications, FPGA images, and RealView Logic Tile IP.

Set SYS_RESETCTRL[8] to generate a software reset.

The reset levels specified by SYS_RESETCTRL[2:0] are:

  • b000 is reserved

  • b001 resets to level 1, CONFIGCLR

  • b010 resets to level 2, CONFIGINIT

  • b011 resets to level 3, DLLRESET (DLL located in FPGA)

  • b100 resets to level 4, PLLRESET (located in ARM926PXP development chip)

  • b101 resets to level 5, PORESET

  • b110 resets to level 6, DOCRESET

  • b111 is reserved.


The Versatile/AB926EJ-S does not differentiate between some of the reset levels. The reset programming for the Versatile/PB926EJ-S has six reset levels to enable more detailed configuration options. The same levels are used in the Versatile/AB926EJ-S to maintain code compatibility between the two platforms.

Figure 3.11. Reset signal sequence

Reset signal sequence

A state machine in the FPGA (see Figure 3.12) uses the value of SYS_RESETCTRL and the external reset signals to sequence the reset signals.

Figure 3.12. Programmable reset level

Programmable reset level

See Table 3.4 for a description of the reset signals.