Table 3.3 lists the default levels of reset that results from external sources.
|External source||Reset level||Hardware nBOARDPOR generated||Reset generatedfor CPU, memory and peripherals|
|RESET pushbutton or software reset||6||No||Yes|
Figure 3.11 shows the activity on the reset signals at different levels of reset.
The level of reset that results from pressing the RESET pushbutton or generating a software reset can be configured by the SYS_RESETCTRL register. The ability to configure the reset level gives greater flexibility in designing applications, FPGA images, and RealView Logic Tile IP.
Set SYS_RESETCTRL to generate a software reset.
The reset levels specified by SYS_RESETCTRL[2:0] are:
b001resets to level 1, CONFIGCLR
b010resets to level 2, CONFIGINIT
b011resets to level 3, DLLRESET (DLL located in FPGA)
b100resets to level 4, PLLRESET (located in ARM926PXP development chip)
b101resets to level 5, PORESET
b110resets to level 6, DOCRESET
The Versatile/AB926EJ-S does not differentiate between some of the reset levels. The reset programming for the Versatile/PB926EJ-S has six reset levels to enable more detailed configuration options. The same levels are used in the Versatile/AB926EJ-S to maintain code compatibility between the two platforms.
A state machine in the FPGA (see Figure 3.12) uses the value of SYS_RESETCTRL and the external reset signals to sequence the reset signals.
See Table 3.4 for a description of the reset signals.