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3.3.5. Reset timing

Figure 3.13 shows the power-on reset sequence.

nBOARDPOR is generated at power-up and connected to the FPGA by the nTRST signal.

Figure 3.13. Power-on reset and configuration timing

Power-on reset and configuration timing

On power up, nTRST is asserted to guarantee the embedded ICE macrocell is reset in the ARM926PXP development chip.