The FPGA provides the bus interface to an external OTG243 USB controller. A block diagram of the USB interface is shown in Figure 3.30.
The internal registers of the controller are memory-mapped
onto the AHBM2 bus at
OTG243 USB ports 2 and 3 are not used on the Versatile/AB926EJ-S.
The signals associated with the USB interface is shown in Table 3.16.
|DPx||D+ data line|
|DMx||D- data line|
|USBETHD[31:0]||Data lines of USB controller|
|USBETHA[8:2]||Address lines of USB controller|
|USBOT[1:0]||DMA end of transfer for channel 1 and 0|
|USBnCS||Controller chip select|
|USBnRD||Read strobe to controller|
|USBnWR||Write strobe to controller|
|USBnINT||Controller interrupt out|
|USBWAKEUP||FPGA drives this signal HIGH to wake up the controller|
|REFCLK24MHZ2U||24MHz reference clock to controller|
|nOC||Over current detect (disconnects power to USB2 and USB3)|
|USBEOT||DMA end of transfer.|
|nEXVBO||Connects additional power to the OTG (VBUS)|
|VBP||Connects additional power to the OTG (VBUS)|
|VBUS||If the OTG is in slave mode, this is the incoming 5V digital power supply from the cable.|
For a full description, refer to the datasheet for the TransDimension OTG243.