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3.17. USB interface

The FPGA provides the bus interface to an external OTG243 USB controller. A block diagram of the USB interface is shown in Figure 3.30.

The internal registers of the controller are memory-mapped onto the AHBM2 bus at 0x10020000.

Figure 3.30. OTG243 block diagram

OTG243 block diagram

OTG243 USB ports 2 and 3 are not used on the Versatile/AB926EJ-S.

The signals associated with the USB interface is shown in Table 3.16.

Table 3.16. USB interface signal assignment
Signal nameDescription
DPxD+ data line
DMxD- data line
USBETHD[31:0]Data lines of USB controller
USBETHA[8:2]Address lines of USB controller
USBOT[1:0]DMA end of transfer for channel 1 and 0
USBnCSController chip select
USBnRDRead strobe to controller
USBnWRWrite strobe to controller
USBnINTController interrupt out
nRESETController reset
USBWAKEUPFPGA drives this signal HIGH to wake up the controller
REFCLK24MHZ2U24MHz reference clock to controller
nOCOver current detect (disconnects power to USB2 and USB3)
USBEOT[0]DMA end of transfer.
USBDRQ[0]DMA request.
USBDACK[0]DMA acknowledge.
nEXVBOConnects additional power to the OTG (VBUS)
VBPConnects additional power to the OTG (VBUS)
VBUSIf the OTG is in slave mode, this is the incoming 5V digital power supply from the cable.


For a full description, refer to the datasheet for the TransDimension OTG243.

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