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B.2. Clock rate restrictions

The clock rates specified in Table B.4 are the maximum values that can be used for reliable operation.

The ICS307 programmable oscillators OSC0 and OSC1 can be programmed to deliver very high clock signals (200MHZ). The only ARM926PXP development chip clock input that can function at this frequency is PLLCLKEXT.

Also, the settings for VCO divider, output divider, and output select values are interrelated and must be set correctly. Some combinations of settings do not result in stable operation. For more information on the ICS clock generator and a frequency calculator, see the ICS web site at

Reliable use of DMA might require lowering the bus frequency. See the readme.txt file for more information on timing. For timing information for ARM926PXP development chip signals, see the ARM926PXP development chip Reference Manual.

Table B.4. Maximum clock rates
FunctionSignalDescriptionMaximum frequency
CPU coreCPUCLKThis internal clock is normally generated from the PLL by multiplying up the XTALCLKEXT frequency. The ARM926PXP development chip can, however, be configured to use PLLCLKEXT as CPUCLK.210MHz
SDRAMMPMCCLKThis clock, together with the delay settings in the MPMC, determines the access time for the dynamic memory.70MHz
Internal AMBA busHCLKThis is an internal clock generated from CPUCLK and the HCLK divider. 70MHz
External AMBA busHCLKEXT

This internal clock is generated from HCLK and the HCLKEXT divider. It clocks the output part of the AMBA M2 bridges in synchronous mode (with HCLKM2). This clock is at the same frequency as XTALCLKEXT.


This is an internal clock generated from HCLK and the MBX clock divider. The maximum frequency for MBXCLK is limited by the SDRAM memory devices.

Flash memorySMCLKThis clock is generated from HCLK and the SMC clock divider. It is used to time accesses to static memory.54MHz

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