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3.6. CLCDC interface

A PrimeCell CLCD controller is present in the ARM926PXP development chip.

The Versatile/AB926EJ-S provides a display interface with outputs to:

  • a VGA connector for connecting a VGA or SVGA monitor

  • the peripheral expansion connectors. The AB-IB1 interface board has a connector for an external CLCD kit with a 2.2, 3.8, or 8.4 inch display. The Versatile/AB-IB2 interface board has a built-in 2.5 inch CLCD display.

A PLD and a DAC convert the CLCDC data signals into VGA analog signals. The LCDMODE[1:0] signals select the mapping of CLCD video data to the RGB signals for different resolutions. The video PLD also manages the conversion of the CLCD data into 24 or 16-bit color depth for the VGA output.

Table 3.7 lists the display interface signals and Figure 3.19 shows the architecture of the display interface.

See Color LCD Controller, CLCDC, Appendix E LCD Kits, and the ARM926EJ-S Development Chip Reference Manual for interface details.

Table 3.7. Display interface signals
SignalDescription
CLCD[23:0]LCD panel data. This is the digital RGB signals and synchronization signals.
CLCPLCD panel clock to the interface board.
CLLPLine synchronization pulse (STN)/horizontal synchronization pulse (TFT) to the interface board.
CLFPFrame pulse (STN)/vertical synchronization pulse (TFT) to the interface board.
CLACSTN AC bias drive or TFT data enable output to the interface board.
CLLELine end signal to the interface board.
CLPOWERLCD panel power enable to the interface board.
B[7:0]Blue output signals to D/A converter and to the interface board.
G[7:0]Green output signals to D/A converter and to the interface board.
R[7:0]Red output signals to D/A converter and to the interface board.
RED, GREEN, BLUEAnalog output from D/A converter for red, blue, and green signals to VGA connector.
TSSCLKClock output to touchscreen controller.
TSMOSIData from touchscreen controller.
TSMISOData to touchscreen controller.
TSnDAVTouchscreen controller data available signal.
TSnPENIRQTouchscreen controller pen down interrupt to the secondary interrupt controller in the FPGA.
TSnKPADIRQTouchscreen controller key pressed interrupt to the secondary interrupt controller in the FPGA.
TSnSSTouchscreen controller chip select.
Power control signalsThe nLCDIOON, CLPOWER, PWR3V5VSWITCH, VDDNEGSWITCH, and VDDPOSSWITCH signals can be used by the interface board.
LCDID[4:0]These signals are determined by resistor links on the interface board and indicate the type of display that is attached. The value of these signals can be read from the SYS_CLCD register.
LCDMODE[1:0]These signals select the VGA display resolution. The signals from the FPGA register SYS_CLCD control remapping of the CLCD[23:0] data signals to the B[7:0], G[7:0], and R[7:0] signals to the video DAC.
VGA_CLKThe VGA clock synchronizes the conversion of the B[7:0], G[7:0], and R[7:0] signals into the BLUE, GREEN, and RED analog signals.
VGA_HSYNCThe VGA horizontal synchronization signal.
VGA_VSYNCThe VGA vertical synchronization signal.

Figure 3.19. Display interface

Display interface

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