On-chip peripherals in the ARM926PXP development chip use DMA channels 6-15.
DMA control signals 0-2 are passed to the peripherals in the FPGA. Figure 3.20 shows the DMA architecture.
See also Direct Memory Access Controller.
The DMA control signals for external devices are listed in Table 3.8.
None of the signals for DMA channels 3,4, or 5 are used.
The FPGA peripherals do not use all of the DMA control signals for channels 0, 1, and 2.
The names of DMA control signals change as they pass through the mapping logic in the FPGA.
Burst request inputs to DMACDMACBREQ[1:0] are used by the AACIDMACBREQ is used by the MCI
|DMACLBREQ[2:0]||Last burst request inputs to DMAC (not available for use)|
|DMACSREQ[2:0]||Single request inputs to DMAC DMACSREQ is used by the AACIDMACSREQ[2:1] are not available for use|
|DMACLSREQ[2:0]||Last single request inputs to DMAC (not available for use)|
|DMACCLR[2:0]||Clear outputs from DMAC. These signals acknowledge the request from the corresponding DMASREQ or DMABREQ signalsDMACCLR[1:0] are used by the AACIDMACCLR is used by the MCI|
|DMACTC[2:0]||Terminal count outputs from DMAC (not available for use)|