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3.13. Serial bus interface

The FPGA implements a serial bus interface that is used to identify devices connected to the expansion connector and read and set the time-of-year clock.

Each device on the serial bus has its own slave address. The unique address for each slave on the serial bus is shown in Table 3.12.

Table 3.12. Serial bus addresses
Slave address (7-bit)Slave device
b1010001Static memory module (if present, this is located on the Versatile/AB-IB1 or Versatile/AB-IB2 interface board). See Appendix F Static Memory Expansion Board for details of the serial bus interface to the memory module EEPROM.
b1101000Time-of-year clock

The block diagram of the interface is shown in Figure 3.26.

Figure 3.26. Serial bus block diagram

Serial bus block diagram

Table 3.13. Serial bus signals
SignalDescription
SBSCLOpen-collector clock. This clock is driven by the FPGA, but can be held LOW by an external device if it is not ready to receive or transmit data
SBSDAOpen-collector data signal.

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