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3.15. Synchronous Serial Port, SSP

The ARM926PXP development chip contains a PrimeCell SSP controller that is accessible from the peripheral expansion connector as shown in Figure 3.28.

Figure 3.28. SSP block diagram

SSP block diagram

Table 3.15. SSP signal descriptions

Name

Description

SSPnCS

Chip select to external device connected to SSP controller (see CLCD Control Register, SYS_CLCD)

SSPCLKOUT

PrimeCell SSP clock output to peripheral interface board

SSPRXD

PrimeCell SSP receive data input.

SSPTXD

PrimeCell SSP transmit data output

TSnSS

Chip select to peripheral interface board (see CLCD Control Register, SYS_CLCD)

TSnKPADIRQX

Keypad interrupt signal from interface board

TSnPENIRQ

Pen interrupt signal from interface board

TSnDAV

Data available from interface board (see CLCD Control Register, SYS_CLCD)

The SSP functions as a master interface.See also Synchronous Serial Port, SSP and the ARM PrimeCell Synchronous Serial Port Controller (PL022) Technical Reference Manual.

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