To set up one or more Core Tiles on a Versatile platform baseboard (such as the Versatile/PB926EJ-S shown in Figure 2.4) as a multi-processor development system:
You can fit memory expansion boards to the Core Tile or baseboard if you require additional memory.
Fit one or more sets of Logic Tile and Core Tile to the tile expansion headers on the baseboard.
The Logic Tile provides the interface and arbitration between the baseboard signals and the processor bus on the Core Tile.
For normal operation, a Logic Tile between the Core Tile and the Versatile/PB926EJ-S baseboard provides the interface control. For programming the PLD on the Core Tile however, the Logic Tile must be mounted on top of the Core Tile for the system to configure correctly. This is because the RTCK signal must be floating in configuration mode.
If required, you can connect an Analyzer Tile between the Logic Tile and the Core Tile to enable monitoring of signals between the tiles.
You can also place a Logic Tile and an Interface Tile on the top of the tile stack. The Logic Tile must be loaded with an appropriate image that contains your peripherals.
The connectors on the Interface Tile provide access to the peripherals instantiated in the Logic Tile.
Connect a JTAG debugger to the baseboard (see Connecting a JTAG device to a baseboard).
Connect the CONFIG link on the baseboard.
Supply power to the Versatile/PB926EJ-S (see Supplying power to a Versatile/PB926EJ-S).
Load the appropriate FPGA images into the Logic Tiles. See the application note for details on the image to use. See the Versatile/PB926EJ-S User Guide and Versatile/LT-XC2V4000+ User Guide for details on programming procedures.
Remove the CONFIG link and load your application program.
For details on how to load and run applications on an Versatile/PB926EJ-S system, see the Versatile Platform Baseboard for ARM926EJ-S User Guide.