These headers allow the connection of a RealView Logic Tile to the PB11MPCore. Figure A.14 shows the pin numbers and power-blade usage of the HDRX, HDRY, and HDRZ headers.
The I/O voltage on a RealView Logic Tile (VCCO1 and VCC02) can be changed by removing resistors on the tile and supplying the I/O voltage from either the tile above or the tile below in a tile stack. However, all signals from the PB11MPCore to a RealView Logic Tile use 3.3V I/O levels and all signals from a RealView Logic Tile to the PB11MPCore must use 3.3V I/O levels.
The 5V supply on the headers is to power voltage converters that might be present on the Logic Tile.
The designation used for a multiplexed signal is
X is present when CLKOUTDIV is HIGH and signal
present when CLKOUTDIV is LOW.
See Application Note AN151 for details of the
AXI multiplexing scheme.