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5.7.4. TAP ID registers

The TAP ID code is a 32-bit number divided into multiple fields. Figure 5.10 shows the TAP ID register bit assignments.

Figure 5.10. TAP ID register

Figure 5.10. TAP ID register

You can access the ARM11 MPCore TAP ID code when the PB11MPCore is in Debug mode.

The ARM11 MPCore TAP ID code is:

0x07B37477

Table 5.11 lists how the register divides the number.

Table 5.11. ARM11 MPCore TAP ID register
Bit fieldUseDescriptionValue
[31:28]Revision numberRevision number for the ARM11 MPCore, not necessarily the same as the test chip revision number.0x0
[27:12]Part number

[27:24] prefix.

This is a fixed pattern.

0x7
  

[23:20] IR length.

Identifies the length of the instruction register within the TAP.

0xB
  

[19:12] device code.

This pattern identifies the ARM11 MPCore.

0x37
[11:1]Manufacturer IDHolds the officially registered pattern.b0100 0111 011
[0]Marker bitAlways set to 1, as required by the JTAG specification.b1

See the ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360) for details of the remaining Debug registers in the ARM11 MPCore.

You can access the test chip TAP ID code when the PB11MPCore is in JTAG Configuration mode.

The test chip TAP ID is:

0x17536021

Table 5.12 lists how the register divides the number.

Table 5.12. Test chip TAP ID register
Bit fieldUseDescriptionValue
[31:28]Revision numberRevision number for the test chip, not necessarily the same as the core revision number.0x1
[27:12]Part number

[27:24] prefix.

This is a fixed pattern.

0x7
  

[23:20] IR length.

Identifies the length of the instruction register within the TAP.

0x5
  

[19:12] device code.

This pattern identifies the test chip.

0x36
[11:1]Manufacturer IDHolds the officially registered pattern.b0000 0010 000
[0]Marker bitAlways set to 1, as required by the JTAG specification.b1

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