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B.2.2. AXI bus timings

Table B.2 lists the tile site multiplexed AXI bus timings.

Table B.2. AC Specifications
Clock CycletTScyc30nsCmax=15pF
Output valid time after clock edgetTSov6.771ns 
Output hold time after clock edgetTSoh0.881ns 
Input setup time to clock edgetTSis4.223ns 
Input hold time after clock edgetTSih0.975ns 

Figure B.1 shows the tile site multiplexed AXI timing diagram.

Figure B.1. Tile site multiplexed AXI timing

Figure B.1. Tile site multiplexed AXI timing

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