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C.3.1. Expansion connector

The static memory expansion board uses a 120-way Samtec connector as shown in Figure C.2. The connector pinout is shown in Table C.1.

Note

The numbering of pins on the connector is for the connector as viewed from below.

Figure C.2. Samtec 120-way connector

Figure C.2. Samtec 120-way connector

Table C.1. Static memory connector signals
Pin No.Signal Pin No.Signal
1DATA[0] 23V3
3DATA[1] 43V3
5DATA[2] 63V3
7DATA[3] 83V3
9DATA[4] 10VDDIO[a]
11DATA[5] 12VDDIOa
13DATA[6] 14VDDIOa
15DATA[7] 16VDDIOa
17DATA[8] 181V8
19DATA[9] 201V8
21DATA[10] 221V8
23DATA[11] 241V8
25DATA[12] 26NC
27DATA[13] 28Reserved, not driven
29DATA[14] 30Reserved, not driven
31DATA[15] 32Reserved, not driven
33DATA[16] 345V
35DATA[17] 365V
37DATA[18] 385V
39DATA[19] 405V
41DATA[20] 42Reserved, not driven
43DATA[21] 44Reserved, not driven
45DATA[22] 46Reserved, not driven
47DATA[23] 48Reserved, not driven
49DATA[24] 50Reserved, not driven
51DATA[25] 52Reserved, not driven
53DATA[26] 54Reserved, not driven
55DATA[27] 56Reserved, not driven
57DATA[28] 58Reserved, not driven
59DATA[29] 60Reserved, not driven
61DATA[30] 62SBSCL, E2PROM serial interface clock (3.3V signal level)
63DATA[31] 64SBSDA, E2PROM serial interface data (3.3V signal level)
65ADDR[0] 66nRESET
67ADDR[1] 68nBOARDPOR, asserted on hardware power cycle
69ADDR[2] 70nFLWP, flash write protect. Drive HIGH to write to flash.
71ADDR[3] 72nEARLYRESET, Reset signal. Differs from nRESET in that it is not delayed by nWAIT.
73ADDR[4] 74nWAIT, Wait mode input from external memory controller. Pulled HIGH if not used.
75ADDR[5] 76nBURSTWAIT, Synchronous burst wait input. This is used by the external device to delay a synchronous burst transfer if LOW. Pulled HIGH if not used.
77ADDR[6] 78CANCELWAIT, If HIGH, this signal enables the system to recover from an externally waited transfer that has taken longer than expected to finish. Pulled LOW if not used.
79ADDR[7] 80nCS[4]
81ADDR[8] 82nCS[3]
83ADDR[9] 84nCS[2]
85ADDR[10] 86nCS[1]
87ADDR[11] 88Reserved, not driven
89ADDR[12] 90Reserved, not driven
91ADDR[13] 92Reserved, not driven
93ADDR[14] 94Reserved, not driven
95ADDR[15] 96nCS[0]
97ADDR[16] 98nBUSY, Indicates that memory is not ready to be released from reset. If LOW, this signal holds nRESET active.
99ADDR[17] 100nIRQ
101ADDR[18] 102nWEN
103ADDR[19] 104nOEN
105ADDR[20] 106nBLS[3], Byte Lane Select for bits [31:24]
107ADDR[21] 108nBLS[2], Byte Lane Select for bits [23:16]
109ADDR[22] 110nBLS[1], Byte Lane Select for bits [15:8]
111ADDR[23] 111nBLS[0], Byte Lane Select for bits [7:0]
113ADDR[24] 114CSWIDTH[0], Indicates bus width for fitted part. Not routed through stackable boards.
115ADDR[25] 116CSWIDTH[1], Indicates bus width for fitted part. Not routed through stackable boards.
117ADDRVALID, Indicates that the address output is stable during synchronous burst transfers 118CLK[1]
119BAA, Burst Address Advance. Used to advance the address count in the memory device 120CLK[0]

[a] VDDIO is the data voltage to host. This is not routed through stackable boards


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