Multiplexed AXI buses AXI M and AXI S are connected between the Northbridge and the RealView Logic Tile stack. The user-implemented system in the Logic Tile must co-operate with the system implemented within the Northbridge when using these buses:
- AXI M
The AXI M bus can only be connected to Mux AXI slaves in the Logic Tile stack.
- AXI S
The Mux AXI S bus can only be connected to Mux AXI masters in the Logic Tile stack.
The Northbridge does not contain any slaves attached to the AXI
M bus. The PB11MPCore memory map assigns the top 1GB of address
to this bus, so a RealView Logic Tile can contain user-supplied slaves
that occupy any of this space. The RealView Logic Tile FPGA must
give a response to all transfers that are generated on the Mux AXI
M bus, even those to addresses in the range
The Northbridge never generates these addresses on the AXI M bus. A
separate tile master might, however, generate accesses to this region.
In a system without a fully-decoded address map, there can be addresses at which there are no slaves to respond to a transaction. In such a system, the tile site must provide a suitable error response to flag the access as illegal and also to prevent the system from locking up by trying to access a nonexistent slave.When the tile site cannot successfully decode a slave access, it must route the access to a default slave that returns the DECERR response.An implementation option is to have the default slave also record the details of decode errors for later determination of how the errors occurred. In this way, the default slave can significantly simplify the debugging process.The AXI protocol requires that all data transfers for a transaction are completed, even if an error condition occurs. Therefore any component giving a DECERR response must meet this requirement.
See AXI bus timings for details of the PB11MPCore tile site multiplexed AXI bus timings.