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3.1. Baseboard architecture

Figure 3.1 shows the layout of the baseboard.

Figure 3.1. Baseboard layout

Figure 3.1. Baseboard layout

The major system components and interfaces provided by the baseboard are:

  • a tile site to support ARM Logic Tiles

  • a ARM11 MPCore test chip

  • a Northbridge implementing the major system controllers and interfaces

  • a Southbridge implementing most of the system peripherals

  • a PLD controlling system configuration

  • an 8MB configuration flash to hold the FPGA images

  • 512MB of 32-bit wide (DDR) SDRAM

  • 8MB of 32-bit wide (Pseudo) SRAM

  • 128MB of 32-bit wide NOR flash in two banks of 64MB

  • PISMO connector for up to 256MB (4x64MB) of static memory expansion

  • PCI and PCI Express expansion buses (2 slots for each interface type)

  • USB interface providing 1 OTG and 2 standard USB 2.0 host ports

  • Ethernet interface providing 10Base-T and 100Base-TX support

  • DVI-I interface providing color LCD display and analog VGA monitor support

  • Synchronous Serial Port (SSP) interface

  • 4 x RS232 interfaces with full handshake

  • PS2 keyboard and mouse interfaces

  • audio CODEC interface (AAC)

  • Compact Flash, MMC, SD and Smart Card interfaces

  • general purpose (User) switches and LEDs

  • real-time clock (RTC)

  • time of year clock (TOY) with backup battery

  • programmable clock generators

  • power supplies, voltage control and current monitoring circuitry

  • JTAG config and debug, and Integrated Logic Analyzer (ILA) support

  • USB config port.

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