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1.1.3. Southbridge

The Southbridge implements the following peripheral components and interfaces:

  • Advanced Audio CODEC Interface (PL041)

  • Multimedia Card Interface (PL180)

  • PS2 Keyboard/Mouse Interface (PL050) x 2

  • UART (PL011) x 4

  • Watchdog Module (SP805) x 2

  • Dual-Timer Module (SP804) x 4

  • Synchronous Serial Port (PL022)

  • Smart Card Interface (PL131)

  • General Purpose Input/Output (PL061) x 3

    • sixteen GPIO ports available for external use

    • eight GPIO ports reserved for internal use.

  • Real Time Clock (PL031)

  • Generic Interrupt Controller x 4

  • multiplexed AHB-Lite interface to the Northbridge

  • AHB interface to the baseboard Compact Flash memory.

See Southbridge and the appropriate Technical Reference Manual for details of the PrimeCell components that are integrated in the Southbridge FPGA.


ARM do not support modifications made to the ARM Southbridge FPGA design. Custom peripheral development is only supported when using an attached Logic Tile such as the LT-XC4VLX1000+ for which specific Application Notes are made available on the CD supplied with the PB11MPCore and the ARM website.

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