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5.1. ARM11 MPCore test chip overview

Figure 5.1 shows the top-level functionality of the test chip.

Figure 5.1. Top-level view of ARM11 MPCore test chip

Figure 5.1. Top-level view of ARM11 MPCore test

The main features of the test chip are:

  • an ARM11 MPCore incorporating:

    • four ARM11 MPCore CPUs with Vector Floating Point (VFP) that implement the ARM architecture v6

    • Level 1 (L1) memory subsystem providing 32KB instruction cache and 32KB data cache per CPU

    • JTAG-based debug.

  • L220 Cache Controller incorporating 1MB of Level 2 (L2) unified cache

  • peripheral decoder providing dual 64-bit external AXI buses

  • on-chip PLL with skew control

  • test chip register bank for configuring the ARM11 MPCore test chip

  • design for test (DFT):

    • test control via a TEST_MODE test data register

    • L1 and L2 memory systems Memory Built-In Self Test (MBIST)

    • full chip and boundary scan support

See the ARM11 MPCore Processor Technical Reference Manual (DDI 0360) and the L220 Cache Controller Technical Reference Manual (DDI 329) for further details on these features.

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