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5.5. Memory configuration

The ARM11 MPCore test chip implements Level 1 (L1) and Level 2 (L2) memory subsystems.

The ARM11 MPCore L1 memory subsystem has 32KB of instruction cache and 32KB of data cache per CPU.

The L220 cache controller memory subsystem has 1MB of L2 unified cache.


Software can change the L2 cache size using L2 control registers. See Peripheral decoder for details of the L220 register base address allocation and the L220 Cache Controller Technical Reference Manual (ARM DDI 0329) for details of the L2 control registers.

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