You copied the Doc URL to your clipboard.

5.4. Power supply control

This section describes the ARM11 MPCore test chip power management.

The whole test chip has a single power domain. No Intelligent Energy Management, IEM or adaptive shutdown mechanism is provided. Software can put each ARM11 MPCore CPU in WFI mode. In this case, clock gating ensures that the minimum amount of logic is toggling. Some ARM11 MPCore outputs that provide power information are stored in a specific test chip register. Figure 5.5 shows the test chip power status register bit assignments.

This register is located at address: 0x1F00300C.

Figure 5.5. Test chip power status register

Figure 5.5. Test chip power status register

Table 5.7 lists the test chip power status register bit assignments.

Table 5.7. Test chip power status register
BitsRead/writeReset valueDescription
[31:12]Read as zero, write ignored.0Undefined.
[11:8]ROb0000Reflects the value of the ARM11 MPCore DBGNOPWRDWN [3:0] output. See the ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360) for more information.
[7:6]ROb00Reflects the value of the ARM11 MPCore PWRCTLO3[1:0] output. See the ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360) for more information.
[5:4]RO00Reflects the value of the ARM11 MPCore PWRCTLO2[1:0] output. See the ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360) for more information.
[3:2]RO00Reflects the value of the ARM11 MPCore PWRCTLO1 1:0] output. See the ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360) for more information.
[1:0]RO00Reflects the value of the ARM 11 MPCore PWRCTLO0[1:0] output. See the ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360) for more information.

Was this page helpful? Yes No