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5.3.2. Interrupts

This section describes all the interrupt signals that enter the test chip:

The ARM11 MPCore test chip has the following interrupt lines:

nIRQ[3:0]

CPU legacy IRQ request input lines. Each bit is connected directly to each corresponding CPU:

nIRQ [0] to CPU#[0] nIRQ [1] to CPU#[1] nIRQ [2] to CPU#[2] nIRQ [3] to CPU#[3]

nFIQ[3:0]

CPU private FIQ request input lines. Each bit is connected directly to each corresponding CPU:

nFIQ [0] to CPU#[0] nFIQ [1] to CPU#[1] nFIQ [2] to CPU#[2] nFIQ [3] to CPU#[3]

You can configure each Fast Interrupt Request (FIQ) as a Non Maskable Interrupt (NMI) by using a specific test chip register, the test chip interrupt control register. Figure 5.4 shows the test chip interrupt control register bit assignments.

This register is located at address: 0x1F003004.

Figure 5.4. Test chip interrupt control register

Figure 5.4. Test chip interrupt control register

Table 5.5 describes the test chip interrupt control register.

Table 5.5. Test chip interrupt control register
BitsRead/writeReset valueDescription
[31:4]Read as zero, write ignored0Undefined
[3]RW0Disable the FIQ mask bit in the Current Program Status Register (CPSR) for CPU#[3] so that the FIQ acts as a NMI
[2]RW0Disable the FIQ mask bit in the CPSR for CPU#[2] so that the FIQ acts as a NMI
[1]RW0Disable the FIQ mask bit in the CPSR for CPU#[1] so that the FIQ acts as a NMI
[0]RW0Disable the FIQ mask bit in the CPSR for CPU#[0] so that the FIQ acts as a NMI

INT[15:0]

Distributed Interrupt Controller hardware interrupts. Each bit is connected directly to the corresponding Distributed Interrupt Controller hardware interrupt line.

Dual flip flops, clocked by the output clock of the clock module, CLKOUT, synchronize the nIRQ[3:0], nFIQ[3:0], and INT[15:0] signals.

Interrupt Routing

A total of 32 interrupt lines, INT[31:0] are provided by the Distributed Interrupt Controller in the MPCore multiprocessor. Refer to the ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360) for further details on interrupt handling within the ARM11 MPCore.

Only INT [15:0] are available at the input pins of the ARM11 MPCore test chip for connection to external interrupts, INT [31:16] are used internally. Table 5.6 lists the internal connections of INT[31:16] in the test chip.

Table 5.6. Internal interrupt lines
MPCore interrupt line numberDescription
31Interrupt from L220: Decode error received on master ports from L3
30Interrupt from L220: Slave error received on master ports from L3
29Interrupt from L220: Event counter overflow/increment
28Interrupt from MPCore (SCU): PMUIRQ [11]
27Interrupt from MPCore (SCU): PMUIRQ [10]
26Interrupt from MPCore (SCU): PMUIRQ [9]
25Interrupt from MPCore (SCU): PMUIRQ [8]
24Interrupt from MPCore (SCU): PMUIRQ [7]
23Interrupt from MPCore (SCU): PMUIRQ [6]
22Interrupt from MPCore (SCU): PMUIRQ [5]
21Interrupt from MPCore (SCU): PMUIRQ [4]
20Interrupt from MPCore (CPU3): PMUIRQ [3]
19Interrupt from MPCore (CPU2): PMUIRQ [2]
18Interrupt from MPCore (CPU1): PMUIRQ [1]
17Interrupt from MPCore (CPU0): PMUIRQ [0]
16Tied internally to Gnd

Interrupt routing to the INT [15:0] input pins of the test chip is controlled by values written to the INTMODE[1:0] field in the SYS_PLD_CTRL1 register that allows the selection of three routing modes. Refer to ARM11 MPCore Distributed Interrupt Controller for details.

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