A custom Generic Interrupt Controller (GIC) is implemented in the Southbridge.
|Memory base address|
|Interrupt||nFIQ and nIRQ signals are output to the ARM11 MPCore and the tile site in response to an interrupt from a peripheral.|
|Release version||ARM Custom IP|
|Reference documentation||MPCore Distributed Interrupt Controller in the MPCore Multiprocessor Technical Reference Manual (DDI 0360).|
Four GICs are implemented in the Southbridge:
generates ARM11 MPCore nIRQ
generates ARM11 MPCore nFIQ
generates tile site nIRQ
generates tile site nFIQ
The GICs accept interrupts from peripherals in the Northbridge, Southbridge, on-board peripherals, and the tile site. The GICs generate nFIQ and nIRQ signals to the ARM11 MPCore and the tile site. See Interrupts for details.