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4.11. Generic Interrupt Controller, GIC

A custom Generic Interrupt Controller (GIC) is implemented in the Southbridge.

Table 4.38. Generic Interrupt Controller implementation
PropertyValue
Location Southbridge
Memory base address

0x1E000000 GIC0 generates ARM11 MPCore nIRQ

0x1E010000 GIC1 generates ARM11 MPCore nFIQ

0x1E020000 GIC2 generates tile site nIRQ

0x1E030000 GIC3 generates tile site nFIQ

Interrupt nFIQ and nIRQ signals are output to the ARM11 MPCore and the tile site in response to an interrupt from a peripheral.
DMA
Release versionARM Custom IP
Reference documentationMPCore Distributed Interrupt Controller in the MPCore Multiprocessor Technical Reference Manual (DDI 0360).

Four GICs are implemented in the Southbridge:

GIC0

generates ARM11 MPCore nIRQ

GIC1

generates ARM11 MPCore nFIQ

GIC2

generates tile site nIRQ

GIC3

generates tile site nFIQ

The GICs accept interrupts from peripherals in the Northbridge, Southbridge, on-board peripherals, and the tile site. The GICs generate nFIQ and nIRQ signals to the ARM11 MPCore and the tile site. See Interrupts for details.

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