A custom Generic Interrupt Controller (GIC) is implemented in the Southbridge.
|Memory base address|
|Interrupt||nFIQ and nIRQ signals are output to the Cortex-A8 and the tile site in response to an interrupt from a peripheral.|
|Release version||Custom logic|
|Reference documentation||See Interrupts.|
The four GICs implemented in the Southbridge are assigned as follows:
generates Cortex-A8 nIRQ
generates Cortex-A8 nFIQ
generates tile site nIRQ
generates tile site nFIQ
The GICs accept interrupts from peripherals in the Northbridge, Southbridge, on-board peripherals, and the tile site. The GICs generate nFIQ and nIRQ signals to the Cortex-A8 and the tile site. See Interrupts.