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4.22. USB interface

The USB interface is provided by a Philips ISP1761 controller that provides a standard USB host controller and an On-The-Go (OTG) dual role device controller. The USB host has two downstream ports. The OTG can function as either a host or slave device.

Table 4.90. USB implementation
Location Baseboard (an ISP1761 chip)
Memory base address

0x4F000000 (mapped onto the SMC bus)

Interrupt 61

There are two DMA channels available for the USB controller. These are selectable as 0 or 1. See Single Master Direct Memory Access Controller, SMDMAC.


You must set DMAPSR = b00 in the SYS_DMAPSR register to select this peripheral for DMA access.

Release versionCustom interface to external controller
Reference documentation ISP1761 Hi-Speed Universal Serial Bus On-The-Go controller Product data sheet. See also USB Interface, and the USB test program supplied on the CD.

The ISP1761 has the following features:

  • fully compliant to the USB Rev. 2.0 specification

  • fully compliant to the USB On-The-Go specification

  • includes high-performance USB peripheral controller with integrated Serial Interface Engine, FIFO memory, and transceiver

  • configurable number of downstream and upstream hosts or functions

  • USB host is USB 2.0 compliant and supports 480Mb/s, 12Mb/s, and 1.5Mb/s

  • programmable interrupts and DMA

  • FIFO and 63KB on-chip RAM for USB.

The ISP1761 register base addresses are shown in Table 4.91.

Table 4.91. USB controller base address
0x4F000000Host controller EHCI registers
0x4F00200Peripheral controller registers
0x4F00300Host controller configuration registers
0x4F000370OTG controller registers
0x4F000400Host controller buffer memory (63KB)


The suspend/wakeup signals for the device and host controllers are connected to GPIO2 (see General Purpose Input/Output, GPIO).

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