This chapter describes the memory map and the configuration registers for the peripherals in the baseboard FPGA (Southbridge). It contains the following sections:
For detailed information on the programming interface for the ARM PrimeCells or other ARM IP, see the appropriate technical reference manual. For the DMA channels, interrupt signals, release versions, and any modifications made to the standard part, see the section of this chapter that describes the peripheral or controller.
The peripherals and controllers implemented in the Southbridge are in the standard images distributed by ARM on the Versatile Family CD.
ARM only support the peripherals and controllers provided in the standard image for the Southbridge. Custom IP development should be done using an attached Logic Tile. ARM will provide support for Logic Tiles but cannot provide support for custom peripherals implemented in Logic Tiles.