About Debugging MMUs
DS-5 Debugger provides various features to debug Memory Management Unit (MMU) related issues.
A Memory Management Unit is a hardware feature that controls virtual to physical address translation, access permissions, and memory attributes. The MMU is configured by system control registers and translation tables stored in memory.
A device can contain any number of MMUs. If a device has cascaded MMUs then the output address of one MMU is used as the input address to another MMU. A given translation depends on the context in which it occurs and the set of MMUs that it passes through.
For example, a processor that implements the ARMv7A hypervisor extensions, such as Cortex-A15, includes at least three MMUs. Typically one is used for hypervisor memory, one for virtualization and one for normal memory accesses within an OS. When in hypervisor state, memory accesses pass only through the hypervisor MMU. When in normal state, memory accesses pass first through the normal MMU and then through the virtualization MMU.
To help you debug MMU related issues, DS-5 Debugger enables you to:
convert a virtual address to a physical address
convert a physical address to a virtual address
view the MMU configuration registers and override their values
view the translation tables as a tree structure
view the virtual memory layout and attributes as a table.
You can access these features using the MMU view in the graphical debugger or using the mmu commands from the command line.