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Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.

Table C.1. Issue A

First release


Table C.2. Differences between Issue A and Issue B
Replaced SYSCON with SCC.

Example 3.1

Example 3.2

Table 3.8

All revisions
Added new section about power monitoring.Voltage, current, and power monitoringAll revisions
Change remapped address region for External AXI to 0x0.Table 3.2All revisions
Denoted location of Cortex-A9 MPCore private memory region in memory map and added explanatory Note.Figure 3.2All revisions

Table C.3. Differences between Issue B and Issue C
In the figure Top-level view of the test chip components, the bottom right hand label is changed to HDRX.Figure 2.3All revisions
First sentence changed in Powerup configuration section to reflect board.txt configuration file and ease of understanding.Powerup configurationAll revisions
In Example Typical board.txt file, corrected OSC2 value to 66.67MHz to match value in the ‘Daughterboard OSCLK clock sources’ table.

Table 2.2

All revisions

Note added to Clocks overview figure for ease of understanding.

Figure 2.5All revisions
Test chip registers CDFRW0 and CDFRW1 corrected to CFGRW0 and CFGRW1.Figure 2.6All revisions
Notes added to Test chip PLLs and clock divider logic diagram for ease of understanding.Figure 2.6All revisions
VCO text and formula in Note under Test chip PLLs and clock divider logic figure, placed on two lines for readability.Figure 2.6All revisions
Table updated for clarityTable 2.4All revisions
In the ‘Daughterboard memory map’ figure, REMAP area corrected to 0xE0000000-0xE4000000.Figure 3.1All revisions

Third column in Remap regions table corrected to:


Table 3.2All revisions
In Example Setting the test chip configuration register values from board.txt and Example Alternative values for test chip configuration registers, the reset values are changed to match the reset values of Example Typical board.txt file, for consistency.

Example 3.1

Example 3.2

All revisions
Clock names changed in example to match table for consistency.

Example 3.2

Table 2.3

All revisions
Reset values in Table Test chip SCC register summary, changed to match values in Example Typical board.txt file, for consistency.

Table 3.8

All revisions

Test chip SCC register summary table Entry in board.txt column corrected to:




Table 3.8All revisions

In t able Test chip CFGRW1 Register bit assignments:

  • Bit [7] changed to Reserved

  • The description for Bit[12] is updated.

Table 3.10All revisions

TZPC signals table updated to:




Table 3.12

All revisions
Description of Fclkselect name in table is expanded for ease of understanding.Table 3.9All revisions
Note added to HSB multiplexing figure to explain that AXIMCLK originates from EXTSAXICLK.Figure A.1All revisions

Table C.4. Differences between Issue C and Issue D
Note added above System connect example figure, to state that CoreTile Express A9×4 does not support PCI Express.Figure 2.2All revisions

System interconnect diagram updated:

  • HDRY1 position corrected

  • HDRX1 position corrected

  • HDRX2 position corrected

  • HDRY2 position corrected.

Figure 2.2All revisions
Bullet changed in System interconnect signals to include SCU and ACP, and additional note added to existing note at the end of the bullets.System interconnect signalsAll revisions
Description for OSC1 in Daughterboard OSCCLK clock sources table updatedTable 2.2All revisions
New subsection added on display resolutions and display memory organizationDisplay resolutions and display memory organizationAll revisions
Updated Test chip CFGRW2 Register bits assignments figure to match table.Figure 3.6All revisions

Table C.5. Differences between Issue D and Issue E
Programmers Model updated to reflect the latest templateChapter 3 Programmers ModelAll revisions

Table C.6. Differences between Issue E and Issue F
Updated description of peripheral memory map.Table 3.1All revisions

Updated Preface. Added Timing Diagram section.

Timing diagramsAll revisions
Glossary removed. References and link to ARM Glossary inserted.


All revisions

Configuration chapter shortened.

Information is now in new document ARM® Versatile™ Express Configuration Technical Reference Manual.

Powerup configuration

All revisions
Added new documents to Additional Reading section of Preface. ARM® Versatile™ Express Configuration Technical Reference Manual and ARM® LogicTile Express 13MG Technical Reference Manual.

Additional reading

All revisions
Updated On-chip peripheral memory map.Figure 3.2All revisions

Updated description of TrustZone protection controller.

Updated TZPC information in test chip architecture diagram.

TrustZone protection controller

Figure 2.3

All revisions

Table C.7. Differences between Issue F and Issue G
Added reference to board revision B and board revision C in powerup configuration section.Powerup configuration

Revision B

Revision C

Table C.8. Differences between Issue G and Issue H
Updated OSC2 information.Table 2.2

All revisions

Table C.9. Differences between Issue H and Issue I
Corrected JTAG timing information.Table B.1

All revisions

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