You copied the Doc URL to your clipboard.

Appendix C. Revisions

This appendix describes the technical changes between released issues of this book

Table C.1. Issue A
Change Location Affects

No changes, first release

- -

Table C.2. Differences between Issue A and Issue B
Change Location Affects
Flash memory diagram removed because it is not required in the document. FPGA configuration flash memory interface. All versions
Section DCC FPGA SERIAL INTERFACE reworded. DCC FPGA SERIAL INTERFACE. Version B
Figure altered with daughterboard header names swapped so that site 2 becomes daughterboard site 1. Figure 2.2. All versions
Programmers Model chapter created. Chapter 3 Programmers Model. Version B

Table Trace Port A connector, J11, pin names changed to reflect signal names in schematic:

Pins 9 to 21 and Pin 34.

Table A.1. All versions

Table Trace Port B connector, J12, pin 34 name changed to reflect signal names in schematic.

Table A.2. All versions
Table headings changed from Command name to Register name.

Table A.1.

Table A.2.

Version B
Updated section below SATA connector, J15, J16. Figure A.5. All versions
Caution statement changed to The SATA host. SATA connectors. All versions
Updated section below SATA Host, J15, signal list. Table A.5. All versions
New table added showing HSSTP TX signal FPGA-GTX connectivity. Table A.8. All versions

Table C.3. Differences between Issue B and Issue C
Change Location Affects

System interconnect diagram updated:

  • HDRY1 position corrected.

  • HDRX1 position corrected.

  • HDRX2 position corrected.

  • HDRY2 position corrected.

Figure 2.2. All versions
Clocks section clarified. Clocks. All versions
Minimum design settings for daughterboard operation section added. Minimum design settings for daughterboard operation. All versions
PISMO2 connector section updated.   All versions

Table C.4. Differences between Issue C and Issue D
Change Location Affects

Document updated to latest Technical Publications Element Definition Document (EDD).

All of document. Version D
Signal name nRSTREQ added to daughterboard resets diagram for additional clarification. This signal was formerly called nSRST but not identified in the diagram. Figure 2.6. Version D
Reference in main text to tying CFGDATAOUT HIGH removed. DCC FPGA SERIAL INTERFACE. Version D
Note added to say that signal nRSTREQ must be tied HIGH when the FPGA design does not support the SCC serial interface. DCC FPGA SERIAL INTERFACE. Version D
Replaced NAND_D[7] pin with nRSTREQ. Minimum design settings for daughterboard operation. Version D
Changed signal names from nSRST to nRSTREQ. Minimum design settings for daughterboard operation. Version D
Signals chapter changed to Signal Descriptions appendix to match other documents in the Versatile Express set. Appendix A Signal Descriptions. Version D

Table C.5. Differences between Issue D and Issue E
Change Location Affects
User must program pull-down resistors on TRACEDBGRQ and TRACEDBGACK pins in constraints file. Trace connectors. Version E

Glossary removed. Reference and link to ARM Glossary added to Preface.

Glossary. Version E

Configuration section shortened.

Information is now in new document ARM® Versatile Express Configuration Technical Reference Manual.

FPGA configuration and initialization.

Version E

Added new documents to Additional Reading section of Preface:

  • ARM® Versatile Express Configuration Technical Reference Manual.

  • ARM® CoreTile Express A5x2 Technical Reference Manual.

  • ARM® CoreTile Express A15x2 Technical Reference Manual.

Additional reading.

Version E

Add speed-grade to FPGA description.

About the LogicTile Express 3MG daughterboard.

Overview of the daughterboard hardware.

Version E

Table C.6. Differences between Issue E and Issue F
Change Location Affects
Corrected description of PCI-Express system. PCI-Express Bus (PCIe). All versions

Table C.7. Differences between Issue F and Issue G
Change Location Affects
Removed references to PISMO2. Throughout document. All versions

Was this page helpful? Yes No