This is an overview of the compilation tools support for ARMv4T. This variant of the ARM architecture supports 16-bit Thumb instructions and the ARM instruction set. The following table shows useful command-line options.
| Command-line option | Description |
|---|---|
--cpu=4T | ARMv4 with 16-bit Thumb. |
--cpu= | Where |
--apcs= | Where |
When compiling code for ARMv4T, the compiler supports the 16-bit Thumb instruction set. This provides greater code density, however:
Thumb code usually uses more instructions for a given task, making ARM code best for maximizing performance of time-critical code.
ARM state and associated ARM instructions are required for exception handling
ARM instructions are required for coprocessor accesses including cache configuration (on cached processors) and VFP.
All load and store instructions must specify addresses that are aligned on a natural alignment boundary. For example:
LDRandSTRaddresses must be aligned on a word boundaryLDRHandSTRHaddresses must be aligned on a halfword boundaryLDRBandSTRBaddresses can be aligned to any boundary.
Accesses to addresses that are not on a natural alignment
boundary result in unpredictable behavior.
To control this you must inform the compiler, using __packed,
when you want to access an unaligned address so that it can generate
safe code.
Note
Unaligned accesses, where permitted, are treated as rotated aligned accesses.
- Reference
Using the Compiler:
Compiler Reference:
Assembler Reference: