This is an overview of the compilation tools support for ARMv5TE. This variant of the ARM architecture provides enhanced arithmetic support for Digital Signal Processing (DSP) algorithms. It supports both ARM and 16-bit Thumb instruction sets.The following table shows useful command-line options.
|ARMv5 with 16-bit Thumb, interworking, DSP multiply, and double-word instructions|
|ARMv5 with 16-bit Thumb, interworking, DSP multiply, double-word instructions, and Jazelle® extensions[a]|
[a] The compiler cannot generate Jazelle bytecodes.
When compiling code for ARMv5TE, the compiler:
Supports improved interworking between ARM and Thumb, for example
Performs instruction scheduling for the specified processor. Instructions are re-ordered to minimize interlocks and improve performance.
Uses multiply and multiply-accumulate instructions that act on 16-bit data items.
Uses instruction intrinsics to generate addition and subtraction instructions that perform saturated signed arithmetic. Saturated arithmetic produces the maximum positive or negative value instead of wrapping the result if the calculation overflows the normal integer range.
Uses load (
LDRD) and store (
STRD) instructions that act on two words of data.
All load and store instructions must specify addresses that are aligned on a natural alignment boundary. For example:
STRaddresses must be aligned on a word boundary
STRHaddresses must be aligned on a halfword boundary
STRDaddresses must be aligned on a doubleword boundary
STRBaddresses can be aligned to any boundary.
Accesses to addresses that are not on a natural alignment
boundary result in unpredictable behavior.
To control this you must inform the compiler, using
when you want to access an unaligned address so that it can generate
STR instructions, except
must specify addresses that are word-aligned, otherwise the instruction
generates an abort.
Unaligned accesses, where permitted, are treated as rotated aligned accesses.
Using the Compiler:
Using the Compiler:
- Other information
Technical Reference Manual for your processor.