This information does not apply to ARMv6-M and ARMv7-M profiles.
You must consider what sort of memory your system has at address
the address of the first instruction executed.
This information assumes that an ARM processor begins fetching
0x0. This is the standard behavior
for systems based on ARM processors. However, some ARM processors
can be configured to begin fetching instructions from
There has to be a valid instruction at
startup, so you must have nonvolatile memory located at
the moment of power-on reset. One way to achieve this is to have
ROM located at
0x0. However, there are some drawbacks
to this configuration.
The following example shows a solution implementing ROM/RAM remapping after reset. The constants shown in this example are specific to the Versatile board, but the same method is applicable to any platform that implements remapping in a similar way. Scatter-loading description files must describe the memory map after remapping.
; System memory locations Versatile_ctl_reg EQU 0x101E0000 ; Address of control register DEVCHIP_Remap_bit EQU 0x100 ; Bit 8 is remap bit of control register ENTRY ; Code execution starts here on reset ; On reset, an alias of ROM is at 0x0, so jump to 'real' ROM. LDR pc, =Instruct_2 Instruct_2 ; Remap by setting remap bit of the control register ; Clear the DEVCHIP_Remap_bit by writing 1 to bit 8 of the control register LDR R1, =Versatile_ctl_reg LDR R0, [R1] ORR R0, R0, #DEVCHIP_Remap_bit STR R0, [R1] ; RAM is now at 0x0. ; The exception vectors must be copied from ROM to RAM ; The copying is done later by the C library code inside __main ; Reset_Handler follows on from here