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ARM architecture v7-R

This is an overview of the compilation tools support for ARMv7-R (ARMv7 architecture targeted at the real-time profile). Real-time profiles implement a traditional ARM architecture with multiple modes and support a protected memory system architecture based on an MPU. The ARMv7-R architecture supports both ARM and Thumb instruction sets. The following table shows useful command-line options.

Table 8. Useful command-line options
Command-line optionDescription
--cpu=7ARMv7 with 16-bit Thumb and 32-bit Thumb only (no ARM instructions) but without hardware divide[a]
--cpu=7-RARMv7 real-time profile with ARM, 16-bit Thumb, 32-bit Thumb optional, VFP, 32-bit SIMD support, and hardware divide

Where name is a specific ARM processor. For example:

  • Cortex-R4F for ARMv7 with ARM, 16-bit Thumb, 32-bit Thumb, hardware VFP, hardware divide and SIMD support.

[a] ARM v7 is not a recognized ARM architecture. Rather, it denotes the features that are common to all of the ARMv7-A, ARMv7-R, and ARMv7-M architectures.

Key features

Key features for ARMv7-R:

  • Supports the SDIV and UDIV instructions.

Alignment support

The data alignment behavior supported by the ARM architecture has changed significantly between ARMv4 and ARMv7. An ARMv7 implementation provides hardware support for some unaligned data accesses using LDR, STR, LDRH, and STRH. Other data accesses must maintain alignment using LDM, STM, LDRD, STRD, LDC, STC, LDREX, STREX, and SWP.

You can control the alignment requirements of load and store instructions by using the A bit in the CP15 register c1.

Endian support

You can produce either little-endian or big-endian code using the compiler command-line options --littleend and --bigend respectively.

ARMv7-R supports the following endian modes:


little-endian format


big-endian format.

ARMv7 does not support the legacy BE-32 mode. If you have legacy code for ARM v7 processors that contain instructions with a big-endian byte order, then you must perform byte order reversal.

ARMv7-R supports optional byte order reversal hardware as a static option from reset.