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Vector Floating-Point (VFP) architectures

VFP architectures provide both single and double precision operations. Many operations can take place in either scalar form or in vector form. Several versions of the architecture are supported, including:

  • VFPv2, implemented in:

    • VFP10 revision 1, as provided by the ARM10200E processor

    • VFP9-S, available as a separately licensable option for the ARM926E, ARM946E and ARM966E processors

    • VFP11, as provided in the ARM1136JF-S, ARM1176JZF-S and ARM11 MPCore processors.

  • VFPv3, implemented on ARM architecture v7 and later, for example, the Cortex-A8 processor. VFPv3 is backwards compatible with VFPv2, except that it cannot trap floating point exceptions. It requires no software support code. VFPv3 has 32 double-precision registers.

  • VFPv3, optionally extended with half-precision extensions. These extensions provide conversion functions between half-precision floating-point numbers and single-precision floating-point numbers, in both directions. They can be implemented with any Advanced SIMD and VFP implementation that supports single-precision floating-point numbers.

  • VFPv3-D16, an implementation of VFPv3 that provides 16 double-precision registers. It is implemented on ARM architecture v7 processors that support VFP without NEON.

  • VFPv3U, an implementation of VFPv3 that can trap floating-point exceptions. It requires software support code.


Particular implementations of the VFP architecture might provide additional implementation-specific functionality. For example, the VFP coprocessor hardware might include extra registers for describing exceptional conditions. This extra functionality is known as sub-architecture functionality.

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