IRQ and FIQ interrupts.
You cannot use these intrinsics to change any other
including the mode, state, and imprecise data abort setting. This
means that the intrinsics can be used only if the processor is already
in a privileged mode, because the control bits of the
be changed in User mode.
These intrinsics are available for all processor architectures in both ARM and Thumb state, as follows:
If you are compiling for processors that support ARMv6 (or later), a
CPSinstruction is generated inline for these functions, for example:
If you are compiling for processors that support ARMv4 or ARMv5 in ARM state, the compiler inlines a sequence of
MSRinstructions, for example:
MRS r0, CPSR ORR r0, r0, #0x80 MSR CPSR_c, r0
If you are compiling for processors that support ARMv4 or ARMv5 in Thumb state, or if
--compatibleis being used, the compiler calls a helper function, for example: