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Compiler support for floating-point arithmetic

The compiler provides many features for managing floating-point arithmetic both in hardware and in software.

For example, you can specify software or hardware support for floating-point, particular hardware architectures, and the level of conformance to IEEE floating-point standards.

The selection of floating-point options determines various trade-offs between floating-point performance, system cost, and system flexibility. To obtain the best trade-off between performance, cost, and flexibility, you have to make sensible choices in your selection of floating-point options.

Floating-point arithmetic can be supported, either:

  • In software, through the floating-point library fplib. This library provides functions that can be called to implement floating-point operations using no additional hardware.

  • In hardware, using a hardware Vector Floating Point (VFP) coprocessor with the ARM processor to provide the required floating-point operations. VFP is a coprocessor architecture that implements IEEE floating-point and supports single and double precision, but not extended precision.


    In practice, floating-point arithmetic in the VFP is implemented using a combination of hardware, that executes the common cases, and software, that deals with the uncommon cases, and cases causing exceptions.

Code that uses hardware support for floating-point arithmetic is more compact and offers better performance than code that performs floating-point arithmetic in software. However, hardware support for floating-point arithmetic requires a VFP coprocessor.