Splits LDM and STM instructions performing large numbers of register transfers into multiple LDM or STM instructions, to help reduce interrupt latency on some ARM systems.
--split_ldm is selected, the maximum number of register transfers for
STM instruction is limited to:
Five, for all
LDMs that do not load the PC.
LDMs that load the PC.
Where register transfers beyond these limits are required, multiple
STM instructions are used.
--split_ldm option can reduce interrupt latency on ARM systems
Do not have a cache or a write buffer, for example, a cacheless ARM7TDMI.
Use zero-wait-state, 32-bit memory.
--split_ldm increases code size and decreases performance
STMinstructions are split by default when
--split_ldmis used. However, the compiler might subsequently recombine the separate instructions into an
STMinstructions are split when
Some target hardware does not benefit from code built with
--split_ldm. For example:
It has no significant benefit for cached systems, or for processors with a write buffer.
It has no benefit for systems with non zero-wait-state memory, or for systems with slow peripheral devices. Interrupt latency in such systems is determined by the number of cycles required for the slowest memory or peripheral access. Typically, this is much greater than the latency introduced by multiple register transfers.