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Splits LDM and STM instructions performing large numbers of register transfers into multiple LDM or STM instructions, to help reduce interrupt latency on some ARM systems.

When --split_ldm is selected, the maximum number of register transfers for an LDM or STM instruction is limited to:

  • Five, for all STMs.

  • Five, for LDMs that do not load the PC.

  • Four, for LDMs that load the PC.

Where register transfers beyond these limits are required, multiple LDM or STM instructions are used.


The --split_ldm option can reduce interrupt latency on ARM systems that:

  • Do not have a cache or a write buffer, for example, a cacheless ARM7TDMI.

  • Use zero-wait-state, 32-bit memory.


Using --split_ldm increases code size and decreases performance slightly.


  • --split_ldm only works with ARM® instructions, but it is not guaranteed to work all the time. It does not work with Thumb® instructions.
  • Inline assembler LDM and STM instructions are split by default when --split_ldm is used. However, the compiler might subsequently recombine the separate instructions into an LDM or STM.

  • Only LDM and STM instructions are split when --split_ldm is used.

  • Some target hardware does not benefit from code that is built with --split_ldm. For example:

    • It has no significant benefit for cached systems, or for processors with a write buffer.

    • It has no benefit for systems with non zero-wait-state memory, or for systems with slow peripheral devices. Interrupt latency in such systems is determined by the number of cycles required for the slowest memory or peripheral access. Typically, this is much greater than the latency introduced by multiple register transfers.