All ARM instructions are 32 bits long. Instructions are stored word-aligned, so the least significant two bits of instruction addresses are always zero in ARM state.
Thumb and ThumbEE instructions are either 16 or 32 bits long. Instructions are stored half-word aligned. Some instructions use the least significant bit of the address to determine whether the code being branched to is Thumb code or ARM code.
Before the introduction of 32-bit Thumb, the Thumb instruction set was limited to a restricted subset of the functionality of the ARM instruction set. Almost all Thumb instructions were 16-bit. Together, the 32-bit and 16-bit Thumb instruction set functionality is almost identical to that of the ARM instruction set.
Table 7 describes some of the functional groupings of the available instructions.
Branch and control
These instructions are used to:
These instructions operate on the general-purpose registers. They can perform operations such as addition, subtraction, or bitwise logic on the contents of two registers and place the result in a third register. They can also operate on the value in a single register, or on a value in a register and an immediate value supplied within the instruction.
Long multiply instructions give a 64-bit result in two registers.
Register load and store
These instructions load or store the value of a single register from or to memory. They can load or store a 32-bit word, a 16-bit halfword, or an 8-bit unsigned byte. Byte and halfword loads can either be sign extended or zero extended to fill the 32-bit register.
A few instructions are also defined that can load or store 64-bit doubleword values into two 32-bit registers.
Multiple register load and store
These instructions load or store any subset of the general-purpose registers from or to memory.
Status register access
These instructions move the contents of a status register to or from a general-purpose register.
These instructions support a general way to extend the ARM architecture. They also enable the control of the CP15 System Control coprocessor registers.