The following register names are predeclared when assembling for a Marvell XScale CPU:
XScale accumulator registers.
The following register names are predeclared when assembling for a Marvell XScale CPU with Wireless MMX:
Wireless SIMD data registers (coprocesssor 0).
Usable aliases for coprocessor 1 registers. Use of these aliases is not recommended.
Coprocessor ID register (coprocessor 1 register c0).
Control register (coprocessor 1 register c1).
Saturation SIMD flags (coprocessor 1 register c2).
Arithmetic SIMD flags (coprocessor 1 register c3).
General purpose registers (coprocessor 1 registers c8 - c11).
The register names are case-sensitive and can be mixed case where this matches exactly the Wireless MMX Technology specification.
Control registers, ID register, general-purpose registers
the SIMD flags map onto coprocessor 1. Use the Wireless MMX Technology
TMRC to read and write
to these registers. The coprocessor 1 registers c4-c7 and c12-c15
SIMD data registers (
map onto coprocessor 0 and hold 16x64-bit packed data. Use the Wireless
MMX Technology pseudo-instructions
move data between these registers and the ARM registers.
The assembler supports the
to specify your own register names.