The FPSCR contains all the user-level NEON
and VFP status and control bits. NEON only uses bits[31:27]. The
bits are used as follows:
- bits[31:28]
Are the N, Z, C, and V flags. These are the NEON and VFP status flags. They cannot be used to control conditional execution until they have been copied into the status flags in the CPSR.
- bit[27]
Is the QC, cumulative saturation flag. This is set if saturation occurs in NEON saturating instructions.
- bit[25]
Is the Default NaN (DN) mode control bit:
- 0
Disabled. NaN operands propagate through to the output of a floating-point operation.
- 1
Enabled. Any operation involving one or more NaNs returns the Default NaN.
Note
NEON always uses the Default NaN enabled setting regardless of this bit.
- bit[24]
Is the flush-to-zero mode control bit:
- 0
Flush-to-zero mode is disabled.
- 1
Flush-to-zero mode is enabled.
Flush-to-zero mode can provide greater performance, depending on your hardware and software, at the expense of loss of range.
Note
NEON always uses flush-to-zero mode regardless of this bit.
Flush-to-zero mode must not be used when IEEE 754 compatibility is a requirement.
- bits[23:22]
Control rounding mode as follows:
- 0b00
Round to Nearest (RN) mode.
- 0b01
Round towards Plus infinity (RP) mode.
- 0b10
Round towards Minus infinity (RM) mode.
- 0b11
Round towards Zero (RZ) mode.
Note
NEON always uses the Round to Nearest mode regardless of these bits.
- bits[21:20]
STRIDEis the distance between successive values in a vector. Stride is controlled as follows:- 0b00
STRIDE= 1- 0b11
STRIDE= 2.
- bits[18:16]
LENis the number of registers used by each vector. It is 1 + the value of bits[18:16]:- 0b000
LEN= 1- ...
…
- 0b111
LEN= 8.
- bits[15, 12:8]
Are the exception trap enable bits:
- IDE
input denormal exception enable
- IXE
inexact exception enable
- UFE
underflow exception enable
- OFE
overflow exception enable
- DZE
division by zero exception enable
- IOE
invalid operation exception enable.
This document does not cover the use of floating-point exception trapping. For information see the technical reference manual for the VFP coprocessor you are using.
- bits[7, 4:0]
Are the cumulative exception bits:
- IDC
input denormal exception
- IXC
inexact exception
- UFC
underflow exception
- OFC
overflow exception
- DZC
division by zero exception
- IOC
invalid operation exception.
Cumulative exception bits are set when the corresponding exception occurs. They remain set until you clear them by writing directly to the
FPSCR.- all other bits
Are unused in the basic NEON and VFP specification. They can be used in particular implementations. Do not modify these bits except in accordance with any use in a particular implementation.
To change some bits without affecting other bits, use a read-modify-write procedure.
Note
The use of vector mode is deprecated. Set LEN and STRIDE to
1.
- Concepts
- Reference
The Technical Reference Manual for your VFP coprocessor.