Unprivileged load byte, halfword, or word.
offset}] ; immediate offset (32-bit Thumb encoding only)
offset} ; post-indexed (ARM only)
post-indexed (register) (ARM only)
can be any one of:
unsigned Byte (Zero extend to 32 bits on loads.)
signed Byte (Sign extend to 32 bits.)
unsigned Halfword (Zero extend to 32 bits on loads.)
signed Halfword (Sign extend to 32 bits.)
omitted, for Word.
is an optional condition code.
is the register to load.
is the register on which the memory address is based.
is an offset. If offset is omitted, the address is the value in
is a register containing a value to be used as the offset.
Rmmust not be PC.
is an optional shift.
When these instructions are executed by privileged software, they access memory with the same restrictions as they would have if they were executed by unprivileged software.
When executed by unprivileged software these instructions behave in exactly the same way as the
corresponding load instruction, for example
LDRSBT behaves in the same way as
Offset ranges and architectures
The following table shows the ranges of offsets and availability of these instructions.
Table 10-14 Offsets and architectures, LDR (User mode)
|Instruction||Immediate offset||Post-indexed||+/-Rm a||shift||Arch. b|
|ARM, word or byte||Not available||-4095 to 4095||+/-
|ARM, signed byte, halfword, or signed halfword||Not available||-255 to 255||+/-
|Thumb, 32-bit encoding, word, halfword, signed halfword, byte, or signed byte||0 to 255||Not available||Not available||T2|
You can use -Rm, +Rm, or Rm.
Entries in the Architecture column indicate that the instructions are available as follows:
All versions of the ARM architecture.
The ARMv6T2 and above architectures.