Load Register Exclusive.
is an optional condition code.
is the destination register for the returned status.
is the register to load.
is the second register for doubleword loads.
is the register on which the memory address is based.
is an optional offset applied to the value in Rn.
offsetis permitted only in 32-bit Thumb instructions. If
offsetis omitted, an offset of zero is assumed.
LDREX loads data from memory.
If the physical address has the Shared TLB attribute,
LDREXtags the physical address as exclusive access for the current processor, and clears any exclusive access tag for this processor for any other physical address.
Otherwise, it tags the fact that the executing processor has an outstanding tagged physical address.
PC must not be used for any of
For ARM instructions:
SP can be used but use of SP for any of
Rt2is deprecated in ARMv6T2 and above.
Rtmust be an even numbered register, and not LR.
offsetis not permitted.
For Thumb instructions:
SP can be used for
Rn, but must not be used for any of
Rt2must not be the same register.
The value of
offsetcan be any multiple of four in the range 0-1020.
implement interprocess communication in multiple-processor and shared-memory
For reasons of performance, keep the number of instructions
to a minimum.
The address used in a
must be the same as the address in the most recently executed
available in ARMv6 and above.
STREXH are available in ARMv6K and
All these 32-bit Thumb instructions are available in ARMv6T2
and above, except that
not available in the ARMv7-M architecture.
There are no 16-bit versions of these instructions.
MOV r1, #0x1 ; load the 'lock taken' value try LDREX r0, [LockAddr] ; load the lock value CMP r0, #0 ; is the lock free? STREXEQ r0, r1, [LockAddr] ; try and claim the lock CMPEQ r0, #0 ; did this succeed? BNE try ; no - try again .... ; yes - we have the lock