Parallel halfword Saturate.
is an optional condition code.
is the destination register.
specifies the bit position to saturate to, in the range 1 to 16.
is the register holding the operand.
Halfword-wise signed saturation to any bit position.
SSAT16 instruction saturates
each signed halfword to the signed range -2sat-1 ≤ x ≤ 2sat-1 -1.
You cannot use PC for any register.
You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.
If saturation occurs on either halfword, this instruction
sets the Q flag. To read the state of the Q flag, use an
This ARM instruction is available in ARMv6 and above.
This 32-bit Thumb instruction is available in ARMv6T2 and above. For the ARMv7-M architecture, it is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in Thumb.
SSAT16 r7, #12, r7
SSAT16 r1, #16, r2, LSL #4 ; shifts not permitted with halfword ; saturations