Execute system coprocessor instruction.
is an optional condition code.
is the coprocessor instruction to execute.
is an operand to the instruction. For instructions that take an argument, Rn is compulsory. For instructions that do not take an argument, Rn is optional and if it is not specified,
R0is used. Rn must not be PC.
You can use this instruction to execute special coprocessor instructions such as cache, branch predictor, and TLB operations. The instructions operate by writing to special write-only coprocessor registers. The instruction names are the same as the write-only coprocessor register names and are listed in the ARMv7-AR Architecture Reference Manual. For example:
ICIALLUIS; invalidates all instruction caches Inner Shareable ; to Point of Unification and also flushes branch ; target cache.
SYS ARM instruction is available
in ARMv7-A and ARMv7-R.
SYS 32-bit Thumb instruction
is available in ARMv7-A and ARMv7-R.
There is no 16-bit version of this instruction in Thumb.