Zero extend Halfword.
is an optional condition code.
is the destination register.
is the register holding the value to extend.
is one of:
Rmis rotated right 8 bits.
Rmis rotated right 16 bits.
Rmis rotated right 24 bits.
rotationis omitted, no rotation is performed.
UXTH extends a 16-bit value to a 32-bit value. It does this by:
Rotating the value from
Rmright by 0, 8, 16, or 24 bits.
Extracting bits[15:0] from the value obtained.
Zero extending to 32 bits.
You cannot use PC for any register.
You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.
This instruction does not change the flags.
The following form of this instruction is available in Thumb code, and is a 16-bit instruction:
UXTH Rd, Rm
Rmmust both be Lo registers.
This ARM instruction is available in ARMv6 and above.
This 32-bit Thumb instruction is available in ARMv6T2 and above. For the ARMv7-M architecture, it is only available in an ARMv7E-M implementation.
This 16-bit Thumb instruction is available in ARMv6 and above.