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ARM registers

ARM processors provide general-purpose and special-purpose registers. Some additional registers are available in privileged execution modes.

In all ARM processors, the following registers are available and accessible in any processor mode:

  • 13 general-purpose registers R0-R12.

  • One Stack Pointer (SP).

  • One Link Register (LR).

  • One Program Counter (PC).

  • One Application Program Status Register (APSR).

Note

The Link Register can also be used as a general-purpose register. The Stack Pointer can be used as a general-purpose register in ARM state only.

Additional registers are available in privileged software execution.

ARM processors, with the exception of ARMv6-M and ARMv7-M based processors, have a total of 37 or 40 registers depending on whether the Security Extensions are implemented. The registers are arranged in partially overlapping banks. There is a different register bank for each processor mode. The banked registers give rapid context switching for dealing with processor exceptions and privileged operations.

The additional registers in ARM processors, with the exception of ARMv6-M and ARMv7-M, are:

  • Two supervisor mode registers for banked SP and LR.

  • Two abort mode registers for banked SP and LR.

  • Two undefined mode registers for banked SP and LR.

  • Two interrupt mode registers for banked SP and LR.

  • Seven FIQ mode registers for banked R8-R12, SP and LR.

  • Two monitor mode registers for banked SP and LR.

  • Six Saved Program Status Register (SPSRs), one for each exception mode.

Note

  • The monitor mode registers and one of the SPSRs apply only to the monitor mode and are only present if Security Extensions are implemented.

  • In privileged software execution, CPSR is an alias for APSR and gives access to additional bits.

The following figure shows how the registers are banked in the ARM architecture except ARMv6-M and ARMv7-M:

Figure 2-1 Organization of general-purpose registers and Program Status Registers


In ARMv6-M and ARMv-7M based processors, SP is an alias for the two banked stack pointer registers:

  • Main stack pointer register, which is only available in privileged software execution.

  • Process stack pointer register.

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