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Table Branch Byte and Table Branch Halfword.

TBB [Rn, Rm]

TBH [Rn, Rm, LSL #1]



is the base register. This contains the address of the table of branch lengths. Rn must not be SP.

If PC is specified for Rn, the value used is the address of the instruction plus 4.


is the index register. This contains an index into the table.

Rm must not be PC or SP.


These instructions cause a PC-relative forward branch using a table of single byte offsets (TBB) or halfword offsets (TBH). Rn provides a pointer to the table, and Rm supplies an index into the table. The branch length is twice the value of the byte (TBB) or the halfword (TBH) returned from the table. The target of the branch table must be in the same execution state.


These 32-bit Thumb instructions are available in ARMv6T2 and above.

There are no versions of these instructions in ARM or in 16-bit Thumb encodings.